Principal investigator: Prof. Youn-Long Lin
In contrast to device and local interconnection, global interconnection in two dimensional (2D) system-on-chip (SoC) designs is not scaled as feature size of process technology continues to shrink. Henceforth, global interconnection has become a major speed and power bottleneck in advanced technologies when more functions are accommodated in one single chip. Without further shrink of device sizes, three-dimensional (3D) integrated circuit (IC) chip has been identified as an effective way to achieve better performance in speed and power by scaled global interconnection. Additionally, 3D IC is also a platform for realizing heterogeneous integration. For example, it is feasible to integrate a digital signal processor, an analog signal processor, memory and MEMS using different fabrication technology in one single 3D IC. 3D IC is a promising solution for the next generation of leading-edge electronic designs. However, lacking of EDA tool is one of factors hinders 3D IC from volumes of adoption.
In the past, we have done research on floor-planning for 3D ICs, an evaluation of trade-off among wire-length, number of through-silicon-via (TSV) and placement, redundant through-silicon-via. In the future, we will put focus on the following topics:
IR drop, thermal dissipation, current delivery per package pin and various voltage domains among tiers are important issues in3D IC. The design of power/ground network plays an important role to solve these problems. Because of low resistance, large capacitance, high current delivery and good thermal conductivity in TSV, we will study how to construct a well-structured power distributed network and power TSV to solve the above design issues.
From the aspect of design, the concept of IP reuse should be used in 3D IC to reduce design cost.
Clock skew is an important issue in stacked dies. We need to consider skew issue in pre-bond test which is required to ensure known-good-dies and in post-bond test.
To build a thermal model in 3D IC, we need first to extend the model in 2D to 3D. More importantly, TSV (through silicon via) must be taken into consideration.
Based on the existent wireless test platform, we are developing the urgent technologies of testing and verification for the next-generation VLSI system, with the collaboration with many research institutes, including ITRI, CIC, UCLA, UCSB, and so on. Several focuses are listed as follows:
Based on the wireless test platform, the integration of verification and test can be maximized by utilizing ESL technique, to fulfill the urgent need of system yield and quality in the early design phase.
To replace the traditional monster test equipment, the following infrastructure IP techniques are two key components in the wireless test platform to maximize the efficiency of our wireless test platform: low-cost and high-accurate clock/phase generation circuitry and embedded trace/debug circuitry.
The present wireless test platform built on the SOC technology can be extended to 3D IC to leverage the contactless test communication. By using the die stacking, testing and verification can be further optimized without altering original functionality.
Further advanced built-it self test (BIST) and design-for-test approaches for logic, memory and analog cores are always mandatory to improve the testing and verification.