VIKTOR K. PRASANNA

Charles Lee Powell Chair in Engineering

Professor of Electrical Engineering
Computer Engineering Division
and
Professor of Computer Science

Viktor K. Prasanna (V. K. Prasanna Kumar) ( http://ceng.usc.edu/~prasanna ) is Professor of Electrical Engineering and Professor of Computer Science at the University of Southern California ( USC). He is an associate member of the Center for Applied Mathematical Sciences (CAMS) and a member of USC-Chevron Center of Excellence for Research and Academic Training on Interactive Smart Oilfield Technologies(CiSoft) at USC. His research interests include High Performance Computing, Parallel and Distributed Systems, Reconfigurable Computing, Network Computing and Embedded Systems. He received his BS in Electronics Engineering from the Bangalore University , MS from theSchool of Automation, Indian Institute of Science and Ph.D in Computer Science from the Pennsylvania State University.

Prasanna has published extensively and consulted for industries in the above areas. He is the Steering Committee Co-Chair of the International Parallel & Distributed Processing Symposium ( IPDPS ) [merged IEEE International Parallel Processing Symposium (IPPS) and Symposium on Parallel and Distributed Processing (SPDP)]. He is the Steering Committee Chair of the International Conference on High Performance Computing ( HiPC . In the past, he has served on the editorial boards of the IEEE Transactions on VLSI, IEEE Transactions on Parallel Distributed Computing and the Proceedings of the IEEE. He serves on the editorial boards of the Journal of Parallel and Distributed Computing and the Journal of Pervasive and Mobile Computing. During 2003-'06, he was the Editor-in-Chief of the IEEE Transactions on Computers. He was the founding chair of the IEEE Computer Society Technical Committee on Parallel Processing . He is a Fellow of the IEEE. He is a receipient of the 2005 Okawa Foundation Grant.

Department of Computer Science and Engineering
The Ohio State University
Columbus, OH 43210
Office phone: (614) 292-2770
Office fax: (614) 292-2911
E-mail : zhang at cse dot ohio-state dot edu
URL : http://www.cse.ohio-state.edu/~zhang

Xiaodong Zhang is the Robert M. Critchfield Professor in Engineering, and Chairman of the Department of Computer Science and Engineering at the Ohio State University.

Since 1992, he has established and directed the High Performance Computing and Software Laboratory where he has supervised over 40 graduate students (both MS and Ph.D), post-docs, and visiting scholars. His research interests cover a wide spectrum in the areas of high performance and distributed systems. A common thread among his research projects focuses on fast data accesses and resource sharing with cost- and energy-efficient management at different levels of the memory and storage hierarchies in computer, distributed, and Internet systems. Several technical innovations and research results from his team have been adopted or being developed in commercial products and open source systems with direct impacts to our daily computing operations, including the permutation memory interleaving technique first in the Sun MicroSystems' UltraSPARC IIIi processor for various desktop and server products and then in the Sun's dual-core Gemini Processor, the token thrashing protection mechanism and the Clock-Pro page replacement algorithm for memory management in the Linux Kernel . This list of selected representative papers reflects his long term research efforts.

Xiaodong Zhang was the Program Director of Advanced Computational Research at the National Science Foundation, 2001-2004. He is the associate Editor-in-Chief of IEEE Transactions on Parallel and Distributed Systems, and is also serving on the Editorial Boards of IEEE Transactions on Computers, IEEE Micro, and Journal of Parallel and Distributed Computing. He is an organizer and a lecturer of the Dragon Star Lecture Program offering advanced research classes of computer science and engineering in many Chinese universities for thousands of talented graduate students and young faculty every year.

Xiaodong Zhang received his Ph.D. in Computer Science from the University of Colorado at Boulder in 1989, and his B.S. in Electrical Engineering from Beijing Polytechnic University.

Xiaodong Zhang completed his Master thesis of computer science in Colorado, under the direction of Ralph Slutz (1917-2005), who was a world-class scholar and a computer pioneer.

Jesse Fang, Intel,

Director of Programming Systems Lab

Session Chair: Ali Adl-Tabatabai, Intel

“Parallel Programming Environment: A Key to Translating Tera-Scale Platforms into a Big Success”

Moore 's Law will continue to increase the number of transistors on die for a couple of decades, as silicon technology moves from 65nm today to 45nm, 32 nm and 22nm in the future. Since the power and thermal constraints increase with frequency, multi-core or many-core will be the way of the future microprocessor. In the near future, HW platforms will have many-cores (>16 cores) on die to achieve >1 TIPs computation power, which will communicate each other through an on-die interconnect fabric with >1 TB/s on-die bandwidth and <30 cycles latency. Off-die D-cache will employ 3D stacked memory technology to tremendously increase off-die cache/memory bandwidth and reduce the latency. Fast copper flex cables will link CPU-DRAM on socket and the optical silicon photonics will provide up to 1 Tb/s I/O bandwidth between boxes. The HW system with TIPs of compute power operating in Tera-bytes of data make this a “Tera-scale” platform. What are the SW implications with the HW changes from uniprocessor to Tera-scale platform with many-cores as “the way of the future?” It will be great challenge for programming environments to help programmers to develop concurrent code for most client software. A good concurrent programming environment should extend the existing programming languages that typical programmers are familiar with, and bring benefits for concurrent programming. There are lots of research topics. Examples of these topics include flexible parallel programming models based on needs from applications, better synchronization mechanisms like Transactional Memory to replace simple “Thread + Lock” structure, nested data parallel language primitives with new protocols, fine-grained synchronization mechanisms with HW support, maybe fine-grained message passing, advanced compiler optimizations for the threaded code, and SW tools in the concurrent programming environment. A more interesting problem is how to use such a many-core system to improve single-threaded performance.

Jesse Fang is Director and Chief Scientist of Programming System Lab at Intel/CTG (Corp. Technology Group). Jesse created the lab about 11 years ago, and has been leading the lab to develop programming environment technologies to enable Intel HW uArch research and microprocessor design, and to transfer SW technologies to Intel's Software Solution Group. Before joining Intel in 1995, Jesse was manager of Hewlett-Packet Research Lab compiler team that initiated the Itanium Architecture in 1991. Jesse ran a small start-up between working at HP and Intel. Before HP Labs, Jesse was working as manager or technical leader on parallel/vector compilers at Convex and Concurrent Computer Corporation, Respectively, in 1989 and 1986. Jesse Fang got his Ph.D. in Computer Science at University of Nebraska-Lincoln before he did a post-Doctorate at University of Illinois Urbana-Champaign . He was Assistant Professor at Wichita State University at Kansas before moving to industry. Jesse got his B.S. in Math at Fudan University in Shanghai .